1. Field of the Invention
The present invention relates to a technique for reproducing a clock signal for a lower order group signal at a receiver side in a pulse stuffed synchronizing system.
2. Description of Related Art
In a conventional digital data transmission system, a transmitter converts digital signals into their high-speed digital signal form by time-division multiplexing and a receiver receives and demultiplexes the multiplexed signal to reproduce the original digital signals. The original digital signals to be multiplexed are however supplied from various devices and may not be matched in the clock rate without subjecting to a particular process. For matching or synchronizing the signals, a net synchronizing method or a stuffed synchronizing method may preferably be used.
The stuffed synchronizing method is not designed to directly synchronize the digital signals received from various devices. The stuffed synchronizing method stores the signals to be multiplexed in a memory and then reads out them by use of a common clock signal which is slightly faster than that of the digital signals to align the signals in the timing. A difference between the digital signal and the clock signal is compensated by inserting an extra number of pulses (referred to as stuffed pulses). It is thus needed at the receiver side to identify the position of stuffed pulses for removing the extra pulses.
More specifically, the pulse stuffed synchronizing system is depicted in xe2x80x9cSimple Digital Data Transmissionxe2x80x9d by Makoto Yamashita et al, the Telecommunications Association in Japan, Ver. 4, Jun. 26, 1998. In this reference, there is a case where a clock signal for a lower order group signal and a clock signal for a higher order group signal are not synchronous with each other. At this time, extra pulses are inserted (stuffed) into the lower order group signal at the transmitter side to synchronize the clock signal for the lower order group signal and the clock signal for the higher order group signal. At the receiver side in the pulse stuffed synchronizing system, the extra or stuffed pulses are removed (de-stuffed) and then the clock signal for the lower order group signal is reproduced by a phase synchronization oscillating circuit.
Also, the pulse stuffed synchronizing system is described explicitly in xe2x80x9cWaiting Time Jitterxe2x80x9d by D. L. Duttweiler (The Bell System Technical Journal, Vol. 51, No. 1, January 1972). In this reference, it is described that the stuffed pulses can not fully be removed at the receiver side hence causing jitters.
Particularly, in a conventional pulse stuffed synchronizing method utilized with SONET (synchronous optical network) or SDH (synchronous digital hierarchy) in an advanced digital communication system, the extra pulses are inserted and removed on a byte-by-byte basis. As a result, a greater amplitude of jitter is generated.
A procedure of synchronously multiplexing existing DS3 signals under the SONET standard will now be described. FIGS. 17 to 19 are diagrams showing a frame structure of an STS-1 signal, a frame structure of an STS-1 SPE signal and a byte structure of data signal, respectively.
The SONET specifications are defined in ANSI T1.105-1995 (Synchronous optical network-Basic description including multiplex structure, rates, and formats) and ANSI T1.105.02-1995 (Synchronous optical network-Payload mappings) of the American National Standards Institute. In the standards, the DS3 signal having a nominal bit repetitive frequency of 44.736 Mb/s is accommodated in the STS-1 (synchronous transport signal level 1) signal having a nominal bit repetitive frequency of 51.84 Mb/s. The STS-1 signal is the higher order group signal while the DS3 signal is the lower order group signal. As shown in FIG. 17, the STS-1 signal has a capacity of 810 bytes, 90 bytes in horizontal by 9 rows in vertical and accommodates a single STS-1 SPE (synchronous payload envelope) signal. In the STS-1 signal, the STS-1 SPE is accommodated in the region of a frame other than the overhead region without considering the stuffed pulses and its region is 783 bytes per frame.
Also, the STS-1 signal frame and the STS-1 SPE frame are not always matched relative to each other. As shown in FIG. 17, one frame of the STS-1 SPE signal may be accommodated in two frames of the STS-1 signal. In other words, the head location of the STS-1 SPE signal may be varied in the frame of the STS-1 signal. The head location of the STS-1 SPE signal in the STS-1 signal frame is indicated with pointers H1 and H2 which are accommodated in the overhead region of the STS-1 signal frame.
The STS-1 signal and the STS-1 SPE signal are not always synchronized with each other. For this reason, the STS-1 signal includes positive/zero/negative stuff data in units of bytes. The existence or non-existence of the stuffed pulses is also indicated with the pointers H1 and H2. More specifically, the existence or non-existence of the stuffed pulses is indicated by inverting of specific bits of the pointers H1 and H2.
Also, there is a pointer operation H3. When the positive stuffing is made, one byte of stuffed pulses is inserted after the pointer operation H3. In case of the negative stuffing, STS-1 SPE data is accommodated in one byte of the pointer operation H3. The zero stuffing means that neither the positive stuffing nor negative stuffing is made. In case of the zero stuffing, the stuffed pulses are inserted in one byte of the pointer operation H3 represents and STS-1 SPE data is accommodated in one byte after the pointer operation H3.
As shown in FIGS. 18 and 19, the frame of the STS-1 SPE signal is composed of 783 bytes, 87 bytes in horizontal by 9 rows in vertical, and accommodates a DS3 signal. Since the STS-1 SPE signal and the DS3 signal are not synchronous with each other, the positive stuffing is defined in units of bits. The region of the STS-1 SPE signal where the DS3 signal is accommodated is represented by a combination of stuffed bits s and data bits i regardless of the positive stuffing, and 622 bits per row. The bit s indicates the positive stuffing location where the data of the DS3 signal is usually stored while the stuffed pulses are stored only in a positive stuffing mode. The existence or non-existence of the positive stuffing is indicated by converting all the stuff control bits c to 1. It should be noted that in FIG. 19, o indicates an overhead bit and r indicates a fixed stuff bit which is a type of overhead bit.
When the DS3 signal is accommodated in the STS-1 signal, there are carried out two stages of the stuffing processes, i.e., the positive/zero/negative stuffing process in units of bytes in the STS-1 signal and the positive stuffing process in units of bits in the STS-1 SPE signal. As described previously, the positive/zero/negative stuffing process in units of bytes in the STS-1 signal may generate a greater amplitude of jitter. It is hence crucial to remove such jitter.
For the purpose, an apparatus and a method for mapping and removing jitter are disclosed in Japanese Patent Laid Open Patent Application (JP-A-Heisei 9-505705) as shown by a circuit arrangement of FIG. 1. FIG. 1 is a block diagram showing the structure of a receiving unit (a de-synchronizer) for reproducing the inserted signals including asynchronous data from a high transmission rate synchronization signal in a predetermined clock rate.
Referring to FIG. 1, a first de-stuffing circuit 1 detects the positive/zero/negative stuffing in a received STS-1 signal and carries out the de-stuffing process to remove unnecessary bits such as of the overhead of the STS-1 signal. Thus, the first de-stuffing circuit 1 extract an STS-1 SPE signal 68. Then, a second de-stuffing circuit 12 detects the positive stuffing in the STS-1 SPE signal and carries out the de-stuffing operation to remove unnecessary bits such as the overhead of the STS-1 SPE signal. Thus, the second de-stuffing circuit 12 extract a DS3 signal.
A stuff bit leak circuit 15 produces a data indicating that byte based stuff data 64 of the STS-1 signal detected by the first de-stuffing circuit and bit based stuff data 65 of the STS-1 SPE signal detected by the second de-stuffing circuit are dispersed into bits to remove the stuffed pulses. Then, the circuit 15 outputs the data as a stuff bits leak data 73. Similarly, an overhead delete data generating circuit 16 produces a data indicating that data indicating the number of bytes of the overhead removed by the first and second de-stuffing circuits and data indicating the number of bytes of the unused bits are dispersed in unit of bits and removed. Then, the overhead delete data generating circuit 16 outputs the produced data as overhead delete data 74. Only the DS3 signal extracted from the STS-1 SPE signal is stored in a storage circuit 2 which in turn detects a quantity of stored data and outputs data storage quantity data 75.
First, second and third digital/analog converter circuits 17, 18 and 19 modulates into pulse modulated signals, the stuff bit leak data 73 from the stuff bits leak circuit 15, the overhead delete data 74 from the overhead delete data generating circuit 16, and the data storage quantity data 75 from the storage circuit 2, respectively. An adder circuit 20 adds the three outputs of the first, second 18 and third digital/analog converter circuits 17, 18 and 19. An output of the adder circuit 20 is passed through a low pass filter circuit 603 and fed to a voltage controlled oscillator circuit 604 to control the oscillation clock signal frequency. A clock output 58 outputted from the voltage controlled oscillator circuit 604 is synchronous with the clock signal of the extracted DS3 signal and can be used to read the DS3 signal from the storage circuit 2.
In this manner, the circuit shown in FIG. 17 processes data such that the stuffed pulses are dispersed and removed in units of bits. Thus, variations in the controlled voltage from the voltage controlled oscillator circuit due to the removal of the stuffed pulses is restrained to reduce the generation of jitter.
Also, a stuff multiplexing receiver circuit shown in FIG. 12 is disclosed in Japanese Patent No. 2,697,371. This reference solves the problem that a difference in frequency between a write clock signal and the read clock signal becomes greater when a large number of bits having no data exist in a single frame. In this case, if the frequency difference is large, the drop of pulses from the clock signal which is to be supplied to a PLL circuit is increased so that the amplitude of jitter can be too large. As a result, the PLL circuit can not restrain the jitter. More particularly, the clock signal generated from a transmission line data is divided in frequency into units of frame periods. Also, the clock signal from the voltage controlled oscillator circuit in the PLL is variably divided in frequency into in units of frame periods depending on the existence or non-existence of the stuffed pulses. The two frame periods are then compared to each other in the phase by a phase comparator. The difference between the two frame periods is fed back. In this way, the effect of bits carrying no information in the frame may be avoided.
Next, the stuff multiplexing receiver circuit disclosed in the Japanese Patent No. 2,697,371 will now be described in more detail referring to FIG. 2. The circuit shown in FIG. 2 includes a first and second de-stuffing circuit 1 and 12, as shown in the circuit shown in FIG. 17 and extracts an STS-1 SPE signal 68 and a DS3 signal 52 respectively. The extracted DS3 signal 52 is then stored in a storage circuit 2.
A frame pulse generating circuit 21 divides in frequency the clock signal frequency of the STS-1 signal to produce pluses of each frame cycle of the STS-1 signal. A variable frequency dividing circuit 606 divides a clock output 652 outputted from a voltage controlled oscillator circuit 604 by L which is the number of bits of the DS3 signal accommodated in one frame of the STS-1 signal. It would be apparent that L is a natural number. The number of bits L of the DS3 signal may be varied from one frame to another. For this reason, a variable frequency dividing circuit controlling section 14 calculates L from the stuff data from the first de-stuffing circuit 1 and the second de-stuffing circuit 12 and controls the frequency division ratio of the variable frequency dividing circuit 606.
A phase comparing circuit 601 compares the pulses of each frame cycle of the STS-1 signal received from the frame pulse generating circuit 21 with a clock signal 653 outputted from the variable frequency dividing circuit 606 in phase. The phase comparing circuit 601 transmits the comparing result to a voltage controlled oscillator circuit 604 via an amplifier circuit 602 and a low pass filter circuit 603 to control the oscillation clock signal frequency. The phase comparing circuit 601, the amplifier circuit 602, the low pass filter circuit 603, the voltage controlled oscillator circuit 604, and the variable frequency dividing circuit 606 constitute a phase synchronization oscillator circuit 9 with the frequency division ratio variable. The circuit of the Japanese Patent No. 2,697,371 shown in FIG. 2 carries out the phase comparison in each frame of the STS-1 signal independently of the removal of stuffed pulses, thereby to minimize the effect of jitter caused due to the stuffed pulses.
However, there are the following problems in the apparatus and method for mapping and removing jitter and shown in FIG. 17 and disclosed in the Japanese Laid Open Patent Application (JP-A-Heisei 9-505705).
That is, the oscillation frequency of the voltage controlled oscillator circuit 604 shown in FIG. 17 is determined based on the stuffed bits leak data 73, the overhead delete data 74, and the data storage quantity data 75. For handling the three different types of the data, the circuit arrangement has to be bulky in the size. Also, because the overhead is not related directly to the stuffed pulses, the clock signal can be preferably reproduced without use of the overhead delete data 74. In this respect, the circuit shown in FIG. 17 shall be modified for improvement.
There are the following problems in the stuff multiplex transmitter/receiver circuit of the patent No. 2,697.371 shown in FIG. 18. The number of bits of the DS3 signal in one frame of the STS-1 signal is substantially 5592 in average. Accordingly, when the frequency division ratio L of the phase synchronization oscillator circuit 9 is as high as 5592, the voltage controlled oscillator circuit 604 will fail to restrain the effect of phase noise intrinsic to its circuit, resulting in deterioration of the quality of a reproduced clock signal.
It is desired that the frequency division ratio of the phase synchronization oscillator circuit is not higher than 100. Otherwise, the stuff multiplex transmitter/receiver circuit shown in FIG. 2 is disadvantageous in permitting the reproduced clock signal to have more phase noises.
In conjunction with the above description, a monitoring system of a PCM multiplexing apparatus is disclosed in Japanese Examined Patent Application (JP-B-Showa 63-9697). In this reference, the PCM multiplexing apparatus uses a stuff synchronization system. A stuff rate monitoring circuit is provided for each of channel sections which carries out a stuffing operation to a group of lower order signals to be multiplexed. The stuff rate monitoring circuit monitors whether the stuff rate of the lower order stuffed signals falls within a predetermined range.
Also, a destuffing circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 5-153078). In this destuffing circuit, a signal from a transmission path is converted using a master clock signal provided in the apparatus such that a frame structure is realized of stuff bit inserting positions which are not continuous and are periodical in a constant interval. Moreover, the number of times of the insertion of the stuff bits is averaged. A signal after a re-stuffing operation is supplied to a conventional PLL circuit using a voltage controlled oscillator. Thus, a lower order group signal is smoothed so as to suppress output jitter. In this way, the output jitter of the lower order group signal can be restrained when the stuff bits exist continuously for a few to a few tens of bits in a digital stuff multiplex mode.
Also, a destuff synchronization circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 8-181678). In this reference, a clock signal CK which is subjected to a destuff control is frequency-divided by first xc2xd frequency divider to 1/N frequency divider. Then, a signal WC is selected from the frequency-divided signals by a first selector (31) such that the signal WC does not have a relation of an integer ratio to an inserting bit period of an auxiliary signal which is inserted in a high order group signal S1. An output signal of a voltage controlled oscillator (7) which has the same frequency as the clock signal CK is frequency-divided by second frequency dividers (32 to 34). Then, a signal RC is selected from the frequency-divided signals by a second selector (35) such that the signal RC has the same frequency division ratio as the signal WC. A phase difference between the signal WC and the signal RC is detected by a phase comparator (5) and outputted to an oscillator (7) via a low pass filter (6).
Therefore, an object of the present invention is to provide a clock signal reproducing circuit of a lower order group signal in a pulse stuffed synchronizing system.
Another object of the present invention is to provide a clock signal reproducing circuit of a lower order group signal, in which the effect of jitter can be restrained, even when a large number of stuffed pulses have been inserted.
Still another object of the present invention is to provide a clock signal reproducing circuit of a lower order group signal, in which the phase synchronization oscillator circuit has a small frequency division ratio.
Yet still another object of the present invention is to provide a clock signal reproducing circuit of a lower order group signal, which has a relatively small circuit size.
In order to achieve an aspect of the present invention, a clock signal reproducing circuit in a pulse stuffed synchronizing system which reproduces a lower order group signal from a higher order group signal, includes a destuffing circuit, a storage circuit, a stuff rate determining circuit, a control circuit, a variable frequency divider and a phase synchronization oscillation circuit. The destuffing circuit removes stuff pulses and unnecessary bits from the higher order group signal to output the lower order group signal, and outputs stuff data indicating existence or non-existence of positive stuff or negative stuff in the higher order group signal. The lower order group signal is accommodated in the higher order group signal by inserting the stuff pulses in the lower order group signal. The storage circuit stores the lower order group signal outputted from the destuffing circuit. The stuff rate determining circuit determines a stuff rate from a difference between the number of positive stuffs and the number of negative stuffs to a stuffing possible period of the higher order group signal based on the stuff data outputted from the destuffing circuit. The control circuit outputs a control signal indicating a frequency division ratio based on the stuff rate. The variable frequency divider frequency-divides a clock signal of the higher order group signal based on the control signal outputted from the control circuit. The phase synchronization oscillation circuit reproduces a clock signal of the lower order group signal based on the frequency-divided clock signal outputted from the variable frequency divider. The lower order group signal is read out from the storage circuit in response to the reproduced clock signal of the lower order group signal.
The phase synchronization oscillation circuit multiplies a frequency of the frequency-divided clock signal outputted from the variable frequency divider by N (N is a predetermined positive integer) to reproduce the clock signal of the lower order group signal, when a frequency division ratio of the phase synchronization oscillation circuit is N.
Also, the clock signal reproducing circuit may further includes a separating circuit separates a specific lower order group signal accommodated in the higher order group signal; and an additional frequency divider frequency-divides the clock signal of the higher order group signal. The separated lower order group signal outputted from the separating circuit is supplied to the destuffing circuit, and the frequency-divided clock signal from the additional variable frequency divider is supplied to the variable frequency divider.
Also, the clock signal reproducing circuit may further includes a separating circuit separating a specific lower order group signal accommodated in the higher order group signal. The separated lower order group signal outputted from the separating circuit is supplied to the destuffing circuit.
Also, the control circuit includes a calculating circuit which carries out a calculation based on the stuff rate; a summing circuit summing an output of the calculating circuit for every frequency division period; and a determining circuit determining whether or not an output of the summing circuit is equal to or larger than a predetermined value.
Also, the stuff rate determining circuit includes: a shift register circuit which stores the stuff data in order; a summation calculating circuit which calculates a summation of input data and an output of the shift register circuit; and a multiplying circuit which multiplies an output of the summation calculating circuit by a predetermined value.
Also, the storage circuit includes a storage element, a write address counter, a read address counter and an address control circuit. The storage element stores a signal. The write address counter is driven in response to a write clock signal, and generates a write address to specify a position of the storage element in which an input signal is written. The read address counter is driven in response to a read clock signal and generates a read address to specify a position of the storage element from which an output signal is read out. The address control circuit prevents a writing operation and a reading operation to a same position of the storage element from being carried out at a same time. In this case, the address control circuit controls at least one of the write address counter and the read address counter such that the write address and the read address are apart from each other, when the write address and the read address becomes near to a limit. Also, the address control circuit controls at least one of the write address counter and the read address counter such that the write address and the read address are apart from each other at an initial setting.
In order to achieve another aspect of the present invention, a clock signal reproducing circuit in a pulse stuffed synchronizing system which reproduces a lower order group signal from a higher order group signal, includes a destuffing circuit, a storage circuit, a stuff rate determining circuit, a control circuit, a variable frequency divider and a phase synchronization oscillation circuit. The destuffing circuit removes stuff pulses and unnecessary bits from the higher order group signal to output the lower order group signal, and outputs stuff data indicating existence or non-existence of positive stuff or negative stuff in the higher order group signal. The lower order group signal is accommodated in the higher order group signal by inserting the stuff pulses in the lower order group signal. The storage circuit stores the lower order group signal outputted from the destuffing circuit. The stuff rate determining circuit determines a stuff rate from a difference between the number of positive stuffs and the number of negative stuffs to a stuffing possible period of the higher order group signal based on the stuff data outputted from the destuffing circuit. The control circuit outputs a control signal indicating a frequency division ratio based on the stuff rate. The frequency divider frequency-divides a clock signal of the higher order group signal in a predetermined frequency division ratio. The phase synchronization oscillation circuit frequency-divides the frequency-divided clock signal outputted from the variable frequency divider based on the control signal outputted from the control circuit, to reproduce a clock signal of the lower order group signal. The lower order group signal is read out from the storage circuit in response to the reproduced clock signal of the lower order group signal.
The phase synchronization oscillation circuit multiplies a frequency of the frequency-divided clock signal outputted from the variable frequency divider by N (N is a predetermined positive integer) to reproduce the clock signal of the lower order group signal, when a frequency division ratio of the phase synchronization oscillation circuit is N.
Also, the clock signal reproducing circuit may further includes a separating circuit separates a specific lower order group signal accommodated in the higher order group signal; and an additional frequency divider frequency-divides the clock signal of the higher order group signal. The separated lower order group signal outputted from the separating circuit is supplied to the destuffing circuit, and the frequency-divided clock signal from the additional variable frequency divider is supplied to the variable frequency divider.
Also, the clock signal reproducing circuit may further includes a separating circuit separating a specific lower order group signal accommodated in the higher order group signal. The separated lower order group signal outputted from the separating circuit is supplied to the destuffing circuit.
Also, the control circuit includes a calculating circuit which carries out a calculation based on the stuff rate; a summing circuit summing an output of the calculating circuit for every frequency division period; and a determining circuit determining whether or not an output of the summing circuit is equal to or larger than a predetermined value.
Also, the stuff rate determining circuit includes: a shift register circuit which stores the stuff data in order; a summation calculating circuit which calculates a summation of input data and an output of the shift register circuit; and a multiplying circuit which multiplies an output of the summation calculating circuit by a predetermined value.
Also, the storage circuit includes a storage element, a write address counter, a read address counter and an address control circuit. The storage element stores a signal. The write address counter is driven in response to a write clock signal, and generates a write address to specify a position of the storage element in which an input signal is written. The read address counter is driven in response to a read clock signal and generates a read address to specify a position of the storage element from which an output signal is read out. The address control circuit prevents a writing operation and a reading operation to a same position of the storage element from being carried out at a same time. In this case, the address control circuit controls at least one of the write address counter and the read address counter such that the write address and the read address are apart from each other, when the write address and the read address becomes near to a limit. Also, the address control circuit controls at least one of the write address counter and the read address counter such that the write address and the read address are apart from each other at an initial setting.
In order to achieve still another aspect of the present invention, a clock signal reproducing circuit in a pulse stuffed synchronizing system which reproduces a lower order group signal from a higher order group signal, includes a destuffing circuit, a storage circuit, a stuff rate determining circuit, a first control circuit, a second control circuit, a variable frequency divider and a phase synchronization oscillation circuit. The destuffing circuit removes stuff pulses and unnecessary bits from the higher order group signal to output the lower order group signal, and outputs stuff data indicating existence or non-existence of positive stuff or negative stuff in the higher order group signal. The lower order group signal is accommodated in the higher order group signal by inserting the stuff pulses in the lower order group signal. The storage circuit stores the lower order group signal outputted from the destuffing circuit. The stuff rate determining circuit determines a stuff rate from a difference between the number of positive stuffs and the number of negative stuffs to a stuffing possible period of the higher order group signal based on the stuff data outputted from the destuffing circuit. The first control circuit outputs a first control signal indicating a first frequency division ratio based on the stuff rate. The second control circuit outputs a second control signal indicating a predetermined second frequency division ratio. The variable frequency divider frequency-dividing a clock signal of the higher order group signal based on the first control signal from the first control circuit. The phase synchronization oscillation circuit frequency-divides the frequency-divided clock signal outputted from the variable frequency divider based on the second control signal outputted from the second control circuit, to reproduce a clock signal of the lower order group signal. The lower order group signal is read out from the storage circuit in response to the reproduced clock signal of the lower order group signal.
The phase synchronization oscillation circuit multiplies a frequency of the frequency-divided clock signal outputted from the variable frequency divider by N (N is a predetermined positive integer) to reproduce the clock signal of the lower order group signal, when a frequency division ratio of the phase synchronization oscillation circuit is N.
Also, the clock signal reproducing circuit may further includes a separating circuit separates a specific lower order group signal accommodated in the higher order group signal; and an additional frequency divider frequency-divides the clock signal of the higher order group signal. The separated lower order group signal outputted from the separating circuit is supplied to the destuffing circuit, and the frequency-divided clock signal from the additional variable frequency divider is supplied to the variable frequency divider.
Also, the clock signal reproducing circuit may further includes a separating circuit separating a specific lower order group signal accommodated in the higher order group signal. The separated lower order group signal outputted from the separating circuit is supplied to the destuffing circuit.
Also, the control circuit includes a calculating circuit which carries out a calculation based on the stuff rate; a summing circuit summing an output of the calculating circuit for every frequency division period; and a determining circuit determining whether or not an output of the summing circuit is equal to or larger than a predetermined value.
Also, the stuff rate determining circuit includes: a shift register circuit which stores the stuff data in order; a summation calculating circuit which calculates a summation of input data and an output of the shift register circuit; and a multiplying circuit which multiplies an output of the summation calculating circuit by a predetermined value.
Also, the storage circuit includes a storage element, a write address counter, a read address counter and an address control circuit. The storage element stores a signal. The write address counter is driven in response to a write clock signal, and generates a write address to specify a position of the storage element in which an input signal is written. The read address counter is driven in response to a read clock signal and generates a read address to specify a position of the storage element from which an output signal is read out. The address control circuit prevents a writing operation and a reading operation to a same position of the storage element from being carried out at a same time. In this case, the address control circuit controls at least one of the write address counter and the read address counter such that the write address and the read address are apart from each other, when the write address and the read address becomes near to a limit. Also, the address control circuit controls at least one of the write address counter and the read address counter such that the write address and the read address are apart from each other at an initial setting.
In order to achieve yet still another aspect of the present invention, a clock signal reproducing circuit in a pulse stuffed synchronizing system which reproduces a lower order group signal from a higher order group signal, includes a destuffing circuit, a storage circuit, a stuff rate determining circuit, a first control circuit, a second control circuit, a variable frequency divider and a phase synchronization oscillation circuit. The destuffing circuit removes stuff pulses and unnecessary bits from the higher order group signal to output the lower order group signal, and outputs stuff data indicating existence or non-existence of positive stuff or negative stuff in the higher order group signal. The lower order group signal is accommodated in the higher order group signal by inserting the stuff pulses in the lower order group signal. The storage circuit stores the lower order group signal outputted from the destuffing circuit. The stuff rate determining circuit determines a stuff rate from a difference between the number of positive stuffs and the number of negative stuffs to a stuffing possible period of the higher order group signal based on the stuff data outputted from the destuffing circuit. The first control circuit outputs a first control signal indicating a predetermined first frequency division ratio. The second control circuit outputs a second control signal indicating a second frequency division ratio based on the stuff rate. The variable frequency divider frequency-divides a clock signal of the higher order group signal based on the first control signal from the first control circuit. The phase synchronization oscillation circuit frequency-divides the frequency-divided clock signal outputted from the variable frequency divider based on the second control signal outputted from the second control circuit, to reproduce a clock signal of the lower order group signal. The lower order group signal is read out from the storage circuit in response to the reproduced clock signal of the lower order group signal.
The phase synchronization oscillation circuit multiplies a frequency of the frequency-divided clock signal outputted from the variable frequency divider by N (N is a predetermined positive integer) to reproduce the clock signal of the lower order group signal, when a frequency division ratio of the phase synchronization oscillation circuit is N.
Also, the clock signal reproducing circuit may further includes a separating circuit separates a specific lower order group signal accommodated in the higher order group signal; and an additional frequency divider frequency-divides the clock signal of the higher order group signal. The separated lower order group signal outputted from the separating circuit is supplied to the destuffing circuit, and the frequency-divided clock signal from the additional variable frequency divider is supplied to the variable frequency divider.
Also, the clock signal reproducing circuit may further includes a separating circuit separating a specific lower order group signal accommodated in the higher order group signal. The separated lower order group signal outputted from the separating circuit is supplied to the destuffing circuit.
Also, the control circuit includes a calculating circuit which carries out a calculation based on the stuff rate; a summing circuit summing an output of the calculating circuit for every frequency division period; and a determining circuit determining whether or not an output of the summing circuit is equal to or larger than a predetermined value.
Also, the stuff rate determining circuit includes: a shift register circuit which stores the stuff data in order; a summation calculating circuit which calculates a summation of input data and an output of the shift register circuit; and a multiplying circuit which multiplies an output of the summation calculating circuit by a predetermined value.
Also, the storage circuit includes a storage element, a write address counter, a read address counter and an address control circuit. The storage element stores a signal. The write address counter is driven in response to a write clock signal, and generates a write address to specify a position of the storage element in which an input signal is written. The read address counter is driven in response to a read clock signal and generates a read address to specify a position of the storage element from which an output signal is read out. The address control circuit prevents a writing operation and a reading operation to a same position of the storage element from being carried out at a same time. In this case, the address control circuit controls at least one of the write address counter and the read address counter such that the write address and the read address are apart from each other, when the write address and the read address becomes near to a limit. Also, the address control circuit controls at least one of the write address counter and the read address counter such that the write address and the read address are apart from each other at an initial setting.